When a interrupt occurs, ARM documentation(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/3682.html) says interrupt is disabled till the very end of handlers. When the ARM documentation says that the processor automatically disables the single "Normal IRQ" interrupt, is it the case that all interrupts mapped (via the ARM Interrupt Controller) to the single IRQ gets disabled, or just the one interrupt which was raised is disabled ?
I think so even in nested interrupts case, if interrupts are disabled for brief period to save the CPSR register. Correct me If I am wrong.