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LPC1837 Backup Registers

Jonathan Barnett

The processor has 64 registers (256 bytes) in the RTC power domain

I am using these registers to store temporary data which then gets committed to flash at the end of a transaction.

I can read / write data ok but am getting some odd reads at times.

The Datasheet has specific timings for for writing to the RTC registers..

Do these timings also apply to the Backup Registers as there in the RTC power domain?

Thanks in advance.

Jon.

  • +1

    Hi Jon,

    I think you have to perform an experiment to know the answer to your own question. There is no explicit information regarding this in the datasheet or user manual.

    At first glance, it seems like none of the backup registers are linked to any RTC function. If this is the case, the backup registers are completely independent and only the bus interface clock (BASE_M3_CLK then CLK_M3_BUS) is relevant to timing. There is no need to synchronize with the RTC-oscillator-derived clock when accessing these registers.

    However, in the LPC185x/3x/2x/1x Power domains diagram, the 32 kHz OSCILLATOR is also feeding the BACKUP REGISTERS. Perhaps, this is due to LPC18xx's Event monitor/recorder. The event monitor/recorder can be setup to automatically clear the RTC general purpose (backup) registers when an event occurs on any of the event input channels.

    Regards,

    Goodwin