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Hi
i have some questions on dual Core CortexA9 r3p0 revision.
I am using Cortex A9 r3p0 processor in Our SOC(system on Chip). when i connect to Core 0 and read TTBR0 register i get 0x00004001, but when i connect to Core1 and do read the same TTBR0 register, i get 0x4f352089. is it Okay getting different value.
when i change TTBR0 register value in core 0 , and disconnect to core 0 and again connect to it by soft reset, my changed value disappears and i again get 0x00004001, but same not happens with Core1. in Core 1, say, i change TTBR0 from 0x4f352089 to 0x1
and by disconnecting and again connecting through soft reset, i get changed value means 0x1, not 0x4f352089. what does it mean?
Hello,
did you check the gdb had not set the TTBR0?
Best regards,
Yasuhiko Koumoto.