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How get ARMv7 cache size

John

Hi everybody!!

I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).

In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num sets * num ways * line size.

So, the questions are two:

1) is the computation correct?

2) why the trm (at page 1529) reports: "The parameters NumSets, Associativity and LineSize in these registers define the architecturally visible parameters that are required for the cache maintenance by Set/Way instructions. They are not guaranteed to represent the actual microarchitectural features of a design. You cannot make any inference about the actual sizes of caches based on these parameters. "

Thanks a lot for the support!

John

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  • 0 in reply to Sudeep Holla

    Hi Sudeep,

    thanks for the replay.


    Do you mean that, for instance, banked caches are not visible from those values, right?

    However, the strangeness for me is the sentence "You cannot make any inference about the actual sizes of caches based on these parameters."

    Why?


    BR,

    John

Reply
  • 0 in reply to Sudeep Holla

    Hi Sudeep,

    thanks for the replay.


    Do you mean that, for instance, banked caches are not visible from those values, right?

    However, the strangeness for me is the sentence "You cannot make any inference about the actual sizes of caches based on these parameters."

    Why?


    BR,

    John

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