How AXI Handle unaligned transfer in FIX and INCR mode.
Please consider following example:
CASE 1)
Data bus width = 32 bit
awsize = 1
awlen = 3
Address = 0x03
burst type = FIXED.
CASE 2)
burst type = INCR.
are these invalid transfer or AXI will handle this?
#RTLDesign,#verilog,#digitaldesign,#arm,#AXI4
Both cases look valid to me.
For case 1), the start address that isn't aligned to the transfer width means that this transfer can only access the single byte address 0x3 on WDATA[31:24], so not a 16-bit transfer width because of the unaligned address. And as this is a FIXED burst type, the remaining 3 transfers in the 4-beat burst also remain unaligned and limited to accessing WDATA[31:24].
For case 2), only the first transfer in the 4-beat burst is unaligned, limited to using WDATA[31:24] at address 0x3, and the remaining 3 transfers in the INCR burst can then access address 0x4 (WDATA[15:0]), 0x6 (WDATA[31:24]) and 0x8 (WDATA[15:0]). Note that WSTRB will indicate which byte lanes are being written to in each of the 4 transfers, indicating bytes within the above listed byte lane ranges.