Q1：In the cortex-a7, a phenomenon has been observed where when the DCache attribute is configured as Write-Back, when the CPU reads DDR data, the data is not read into the L2 Cache, but directly into the L1 DCache. Is this phenomenon normal?
Q2：Additionally, the trm document describes the use of a pseudo-random replacement strategy for swapping out L1 and L2. When all ways in a Set are empty, is the filling of ways done randomly, or in the order of way0, way1, and so on?
weibin kong said:Q1：In the cortex-a7, a phenomenon has been observed where when the DCache attribute is configured as Write-Back, when the CPU reads DDR data, the data is not read into the L2 Cache, but directly into the L1 DCache. Is this phenomenon normal?
The TRM (Technical Reference Manual) says in section 7.4:
Data is only allocated to the L2 cache when evicted from the L1 memory system, not when first fetched from the system. The L1 cache can prefetch data from the system without data being evicted from the L2 cache.
See: Optional integrated L2 cache
Which seems to match what you are seeing.