Q1：In the cortex-a7, a phenomenon has been observed where when the DCache attribute is configured as Write-Back, when the CPU reads DDR data, the data is not read into the L2 Cache, but directly into the L1 DCache. Is this phenomenon normal?
Q2：Additionally, the trm document describes the use of a pseudo-random replacement strategy for swapping out L1 and L2. When all ways in a Set are empty, is the filling of ways done randomly, or in the order of way0, way1, and so on?