I have one question.
If the data bus width of the AXI bus is 16 bytes, and a Write Burst transfer is performed with start address = 0x1008, LEN = 0, and SIZE = 0, which bit of WSTB[15:0] should be set to 1?
Could you please answer to this question ?
Hi, this would be as follows
The transaction container is calculated using:
Container_Size = Size * Length = 1 byte
Inside of the transaction container any number of write strobes can be HIGH. This effectively maps to byte lane 8 only.
Outside of the transaction container all write strobes must be LOW. This effectively maps to all byte lanes, expect for byte lane 8.
Hope that helps.
Kind regards,
Ben