Hi,
Working on a SoC with MMU_600. There is a baremetal code which runs in EL3. SMMU is configured for stage 1 and stage 2 translation, VA to PA is one to one mapping.
Configuring Stage 1 only works fine for 4K granule, but when stage 1 and stage 2 are enabled stage 2 fails with a translation fault.
Does EL3 support stage 2 translation ? or any suggestions on configurations.
Thank you,
code snippet Stage 2 config:
S2VMID = sid; S2T0SZ = TTBCR_T0SZ(40); // (64 - 40) S2SL0 = STE_S2SL0_4KBTG0_L1_16_64KBTG0_L2; // 1 S2IR0 = STE_S2IR0_WBC_RA_WA; // 1 S2OR0 = STE_S2OR0_WBC_RA_WA; // 1 S2SH0 = STE_S2SH0_IS; // 3 S2TG = granul_size; // 0 == 4K S2PS = STE_S2PS_40b; // 2 S2AA64 = STE_S2AA64_AARCH64; // 1 S2ENDI = STE_S2ENDI_LE; 0 S2AFFD = STE_S2AFFD_NOFLT; // 1 S2R = 1;
Hi vstehle ,
I am configuring SMMU for stage1 and stage 2 translation, not sure which configuration I have missed.
For 4K granule I am getting stage 2 translation fault, can you provide proper configurations
Dileep D R said:Does EL3 support stage 2 translation ? or any suggestions on configurations.
Dileep D R said:My understanding was SMMU stage-2 translation is independent of CPU EL.
There's a subtly here.
In the CPU architecture, the EL3 translation regime only has S1 translation - not S2.
In the SMMUv3 architecture, in the Stream Table Entry you have to specify the StreamWorld. Broadly, these controls which CPU architecture translation regime you want to replicate. If the StreamWorld is set to EL3 (assuming your SMMU supports it), then the SMMU doesn't support S2 for that Stream.
Have you checked the F_TRANSLATION record, what does it report?
STRW of stream table entry is set to NS-E1.
F_Translation capture,