Hi Experts,
What is the use case of the system error interrupts in ARM V8 and when it will be invoked ? Does it common to all the guest OS running in EL1 ?
Is it the physical input pin change like IRQs or instruction execution like WFE ?
Regards,
Techguyz
SErrors can be triggered in a number of ways, usually either error responses from the memory system (ie SLVERR, DECERR) or via an external pin (triggered by somehting like an L2 cache ECC failure.) Their purpose is to report asynchronous date and instruction fetch errors.
Unlike synchronous errors you generally don;t know which instruction caused the error as the pipeline has moved on, this means that is is difficult to just kill the thread responsible. Often Errors are treated as critical and somethiems trigger s system reset.