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Hello everyone!
I am a developer working on the BSP for an ARM-based chip. The chip I am currently developing is configured in a multi-die environment, with one GIC chip on each of two dies. Each die contains 4 cores, and there is an address offset of 0x2000000000 between the dies.
The software stack is as follows (excluding the components between chipboot and TF-A):
My questions are as follows:
Looking at the GIC kernel driver code (drivers/irqchip/irq-gic-v3.c), it appears to be structured for a single instance. Is there a way to port GIC multichip support without modifying the driver?
Is there a reason why GIC multichip functionality hasn't been considered in the kernel? Were there any attempts to change the code to support a multi-instance structure, or is there any related history?
Thanks you!
I don't know the specifics of the Nvidia case, so can't comment. The way the spec is written is that there is a single GICD register frame, regardless of what the physical implementation looks like. If a design aliased the GICD frame to multiple locations, that's not necessarily non-compliant. A generic drive (unaware of the aliasing) would just know about and use one copy of GICD.
Where it could get interesting is scenarios around things like power management and/or hot swapping.