I’m working on a Zynq 7020 Cortex-A9 AMP setup, where each core runs a separate FreeRTOS instance. The second core starts execution but initially waits at a specific point. Once the first core initializes Ethernet, the second core resumes execution. We are handling SPI (Shared Peripheral Interrupts) correctly with SetCPUID in ScuGic, and we have enabled the USE_AMP directive in the BSP settings for the second core. Our QSPI flash contains FSBL, the FPGA BIT file, and the software for the first core, and everything boots properly. We attach the second core via debug, and both cores operate without issues in this setup.
Both cores function independently when tested separately without USE_AMP, and each can send broadcast messages over Ethernet from different IP addresses. Linker scripts have been configured properly, and RAM has been correctly divided between the two cores.
The problem is that the second core only receives a single interrupt from the PL-based IPs, and then no further interrupts are received. However, PS interrupts, such as EMAC, Global Timer, and TTC Timer, work normally. We suspect this is related to L2 cache issues because when debugging the second core step by step through boot.S, modifying, skipping, or executing certain L2 cache-related instructions causes the first core to crash while the second core continues running fine. With USE_AMP enabled, we either receive a single PL interrupt or none at all.
We are trying to determine whether this is caused by L2 cache mismanagement, incorrect interrupt routing, or a missing synchronization step. Any insights or debugging suggestions would be highly appreciated.