Hi there,
I am getting a hard fault for accessing an unaligned memory address with STR single word access on a cortex M4 processor (Infineon XMC4500 F100k1024). Cortex M4 manual says that:
What could be the possible reason of this fault?
My code is as follows. It throws an exception at STR.
PRESERVE8 THUMB Stack EQU 0x00000100 AREA STACK,NOINIT,READWRITE,ALIGN=3 StackMem SPACE Stack AREA RESET,DATA ,READONLY EXPORT __Vectors __Vectors DCD StackMem + Stack DCD Reset_Handler ALIGN AREA |.text|,CODE,READONLY, ALIGN=2 ENTRY EXPORT Reset_Handler Reset_Handler MOV R5 , #0x3c94 MOVT R5 , #0x2000 MOV R4 , #0x123 STR R4 , [R5] STOP B STOP END
Hello.
it seems to be very strange.
Did you check the memory map whether the __Vectors area had been located at address 0?
Best regards,
Yasuhiko Koumoto.
Hello,
let me confirm that the sample code which you mentioned showed an unaligned access?
Because the address is 0x20003c94, I think is is word aligned.
Had the sample code thrown the hard fault?
I cannot believe.
Actually I checked at 0x20003C92. It threw hard fault on that. I changed it to 94 to confirm that unaligned access is causing problem. 0x20003C94 worked. You noticed it correctly.
It is strange nonetheless, that cortex-M4 is throwing a hard fault on single word unaligned access. What do you think about the cause of this problem? Is it a manufacturing defect or something else.
Thanks for your reply.
Yes. I did check memory map. Everything was perfect. There was a built in issue with this processor so I manually configured CCR register which had an unalign trap bit. I simply cleared that bit and it worked. However, in documentation, the reset value of that bit was 0 but actually on reset it wasn't zero so I had to do a reset manually.
Added following in my assembly code:
thank you and now I understood.
According to the XMC4500 Reference Manual (V1.5 2014-07), it is described that the UsageFault is generated by an unaligned access when CCR.UNALIGN_ TRP=1.
It would be strange that the hard fault was generated.
Also, in the RM, the reset value of CCR is described as 0x00000200 (i.e. UNALIGN_ TRP=0).
As you say, it might be a manufacturing defect.
By the way, what is the reset value of CCR of the part?
Otherwise it maybe SRAM problem.
By some reasons, the clock supply to the DRAM would be delayed (of course, this is a defect).
How about taking a long wait period until accessing to the SRAM?
Hi,
Default value for CCR register should be 0x200, but after my reset, CCR has a value of 0x218. This makes CCR.UNALIGN_ TRP=1 and hence the problem. I think it is a manufacturing defect. Initially I thought that it was an SRAM problem. But I was using cached SRAM and I don't have any previous experience with cache, so I didn't look for it. And sorry for confusing the fault. It was a usage fault.
Thank you very much for your opinion. I'm grateful.
Regards
Saqib Ahmed
Hello Saqib,
thank you for your explanations.
I think it would be a manufacturing defect, too.