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Cortex M4 Unaligned access with STR single word access

Saqib Ahmed

Hi there,

I am getting a hard fault for accessing an unaligned memory address with STR single word access on a cortex M4 processor (Infineon XMC4500 F100k1024). Cortex M4 manual says that:

Unaligned support is only available for load/store singles (LDR, STR). Load/store double already supports word aligned accesses, but does not permit other unaligned accesses, and generates a fault if this is attempted. 

What could be the possible reason of this fault?

My code is as follows. It throws an exception at STR. 


     PRESERVE8
     THUMB
Stack EQU 0x00000100

     AREA STACK,NOINIT,READWRITE,ALIGN=3
             
StackMem SPACE Stack

     AREA RESET,DATA ,READONLY
     EXPORT __Vectors
             
__Vectors
     DCD StackMem + Stack
     DCD Reset_Handler
     ALIGN

     AREA |.text|,CODE,READONLY, ALIGN=2

ENTRY
     EXPORT Reset_Handler     
Reset_Handler

     MOV R5 , #0x3c94
         MOVT R5 , #0x2000
     MOV R4 , #0x123
         STR R4 , [R5]
         
STOP
     B STOP
     END
    
   
Parents
  • 0 in reply to Saqib Ahmed

    Hello.

    thank you and now I understood.

    According to the XMC4500 Reference Manual (V1.5 2014-07), it is described that the UsageFault is generated by an unaligned access when CCR.UNALIGN_ TRP=1.

    It would be strange that the hard fault was generated.

    Also, in the RM, the reset value of CCR is described as 0x00000200 (i.e. UNALIGN_ TRP=0).

    As you say, it might be a manufacturing defect.

    By the way, what is the reset value of CCR of the part?

    Otherwise it maybe SRAM problem.

    By some reasons, the clock supply to the DRAM would be delayed (of course, this is a defect).

    How about taking a long wait period until accessing to the SRAM?

    Best regards,

    Yasuhiko Koumoto.

Reply
  • 0 in reply to Saqib Ahmed

    Hello.

    thank you and now I understood.

    According to the XMC4500 Reference Manual (V1.5 2014-07), it is described that the UsageFault is generated by an unaligned access when CCR.UNALIGN_ TRP=1.

    It would be strange that the hard fault was generated.

    Also, in the RM, the reset value of CCR is described as 0x00000200 (i.e. UNALIGN_ TRP=0).

    As you say, it might be a manufacturing defect.

    By the way, what is the reset value of CCR of the part?

    Otherwise it maybe SRAM problem.

    By some reasons, the clock supply to the DRAM would be delayed (of course, this is a defect).

    How about taking a long wait period until accessing to the SRAM?

    Best regards,

    Yasuhiko Koumoto.

Children
  • 0 in reply to Yasuhiko Koumoto

    Hi,

    Default value for CCR register should be 0x200, but after my reset, CCR has a value of 0x218. This makes CCR.UNALIGN_ TRP=1 and hence the problem. I think it is a manufacturing defect. Initially I thought that it was an SRAM problem. But I was using cached SRAM and I don't have any previous experience with cache, so I didn't look for it. And sorry for confusing the fault. It was a usage fault.

    Thank you very much for your opinion. I'm grateful.

    Regards

    Saqib Ahmed

  • 0 in reply to Saqib Ahmed

    Hello Saqib,

    thank you for your explanations.

    I think it would be a manufacturing defect, too.

    Best regards,

    Yasuhiko Koumoto.