Hello ARM experts:
In chapter K14.5.4 Ordering of Memory-mapped device control with payloads of ARMv8 reference manual(version:K.a), one of the example is:
• When a DMA peripheral has written to a buffer of data in memory, and the processing element is reading a status register to determine that the DMA transfer has completed, and then is reading the data.
It says "A DMB, or load-acquire, is not sufficient as this problem is not solely concerned with observation order, since the polling read is actually a read of a status register at a Completer, not the polling a data value that has been written by an observer."
So, for this case, the code is therefore:
P1 WAIT ([X4] == 1) ; X4 contains the address of the status register, ; and the value '1' indicates completion of the DMA transfer DSB <domain> LDR W5, [X2] ; reads data from the data buffer
But I think dmb is enough since dmb ensures no reordering.When P1 observes [4] = 1, it exits the loop and than reads data from the data buffer.
So what do I misunderstand？Thanks
Hi digital_kevin,
You are right, in most of the cases.
See https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=22ec71615d824f4f11d38d0e55a88d8956b7e45f
Hi vstehle,
I have read the link. The link mentioned "other-multi-copy atomicity", but I didn't find the definiton in the Spec.
what is the difference between "multi-copy atomicity" and "other-multi-copy atomicity"?
The definition is (a bit hidden) in the Arm ARM:
B2.2.4 Requirements for multi-copy atomicity (..) The Arm memory model is Other-multi-copy atomic. Other-multi-copy atomic This is a Memory Write effect from an observer that, if observed by a different observer, is then observed by all other observers that access the location coherently.
B2.2.4 Requirements for multi-copy atomicity
(..) The Arm memory model is Other-multi-copy atomic.
Other-multi-copy atomic
This is a Memory Write effect from an observer that, if observed by a different observer, is then observed by all other observers that access the location coherently.
In multi-copy atomicity, even the writer is concerned.
If I understand Correctly,
multi-copy atomicity means a Memory Write effect from an observer that, if observed by a different observer, is then observed by all observers(including the observer which issues the write) that access the location coherently.
Another question, what does the "coherently" means? Can I assume that all the observers are in the same inner-shareable domian?
Does the same thing apply for the example in K14.4? Or is there something different about this case? Thanks
Hi Alwin Joshy,
Do you mean to replace the DSB instruction in "K14.4 Using a mailbox to send an interrupt" by a DMB OSHST?
As per Will's commit message above, this is now possible, in most of the cases, but some exceptions remain:
Memory-mapped, DMA-capable peripherals that are private to a CPU (i.e. inaccessible to other CPUs) still require the DSB.
Therefore you need to consider your specific case carefully.
Yep, that's the one. Thanks for the clarification.