Env: cortex-a53 dual core
Q: core 0 setup page table at address 0x10000000, and enable inner&outer shareable attr first,
could core1 reuse the same page table by just set TTBR_EL3 as 0x10000000?
met sync exceptions anyway, could you offer some suggestion to debug ?
thanks.
ok I'll check and report. by the way, since it's a dual core systemis there anything to do with SMPxxx registers?