Architectures and Processors forum shared page table between dual cores

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shared page table between dual cores

WatterCutter 7 months ago

Env: cortex-a53 dual core

Q: core 0 setup page table at address 0x10000000, and enable inner&outer shareable attr first,

could core1 reuse the same page table by just set TTBR_EL3 as 0x10000000?

met sync exceptions anyway, could you offer some suggestion to debug ?

thanks.

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Martin Weidmann 7 months ago +1 verified

Yes, multiple cores can (and often do) share the same set of translation times. It's expected that you have the same other settings (e.g. in TCR_ELx, MAIR_ELx...) on all the cores using the tables so that...

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0 WatterCutter 7 months ago in reply to Martin Weidmann

ok I'll check and report. by the way, since it's a dual core systemis there anything to do with SMPxxx registers?
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0 WatterCutter 7 months ago in reply to Martin Weidmann

ok I'll check and report. by the way, since it's a dual core systemis there anything to do with SMPxxx registers?
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