i want to define a region in the peripheral area (address=0x40000000-0x40001000) which will be cacheable area.
this is actually a memory which the CPU will be fetching/loading/storing from it.
i understand that i need to define an MPU unit for that and this is what i do in order to define this region as cacheable area:
void configure_mpu_for_peripheral_execution(void) {
// Disable the MPU before configuration
ARM_MPU_Disable();
//set MAIR regs
MPU->MAIR0 = 0xFFFFFFFF;//normal memory , cache able
MPU->MAIR1 = 0xFFFFFFFF;//normal memory , cache able
// Configure the MPU region for peripheral memory to allow execution
ARM_MPU_SetRegion(
0x0,//RNR - region number 0
(SRAM_CNTRL_0_START_ADDR) + (1<<1), // RBAR - base address is the sram start address. 1<<1 for allowing access from all priv accesses
(SRAM_CNTRL_0_START_ADDR & 0xffffffE0) + 0x1000 + 1//RSAR - end address is the sram base address + 0x1000. 1<<0 for region enabling
);
in my booty code i call the "cache_enable" function so the cache shall be enabled.
i see the M55 successfully fetching from this memory (AXI bus) and also loading/storing to it.
i have doubts regarding the cache. not sure i see any effect of the cache and i suspect that it is not treated as cached area.
am i doing something wrong in the code above? is there any other configuration that shall be done? is there a register or other way to see if the cache is activated and is taking into consideration this area?