Hi
When I test Cortex-R52 with GIC500 (GICv3), I find an issue.
The interrupt is handled by the following order:
1. save context
2. read ICC_IAR0, get INTID
3. jump to ISR of the associated INTID
4. write ICC_EOIR0
5. restore context
The IRQ is unmasked before writing ICC_EOIR0.
When an IRQ is triggered frequently, I find the CPU will never goes to the last step - restore context. Could you explain the reason for that ?
BR, Grace