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In A53, is the L1 D cache way allocation random?

User_0182

Hi everybody, 

I am trying to read back data in the A53 L1 data cache through the technique in TRM "6.7 Direct access to internal memory".

I noticed even when I read a block of memories sequentially, the values I read back showed the way 0-3 allocation is unpredictable. 

Is it randomly allocated? I heard of something being random somewhere. 

Thank you. 

User_0182

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