hi,
I am new to arm virtualization and little confused by below diagram
Till now what i have understood is that with hypervisor running in EL2 we can route physical interrupt to el2 by configuring certain register, then el2 can generate the virtual IRQ and send to guest OS running in el1.
As seen in above diagram vIRQ is a physical line from gic to CPU ,but both IRQ and vIRQ have same vector table entry.
If we go by little analogy FIQ and IRQ are also h/w signal from GIC to CPU and they have separate vector table entry
similarly i thought as VIRQ and VFIQ are also h/w signal from GIC to CPU so they should also have a separate entry in Vector table entry . But that is not the case i was checking my guest-os code it had only standard ARM Vector table and that seem logically .
So is it like my understanding of above diagram is not correct, meaning VIRQ and VFIQ are not Physical lines from GIC to CPU.
or
They are HW signal but there is some more HW logic ,which checks which HW line generate interrupt IRQ or VIRQ :
If VIRQ signal is generated ,switch CPU to EL1 and then route VIRQ to CPU IRQ
If IRQ signal is generated ,switch CPU to EL2 and then route IRQ to CPU IRQCan you please through some light on this ,as to how we don't need separate vector table entry for vIRQ or vFIQ.RegardsSN
They are actually routed to separate vector table entries, because the physical IRQ or FIQ will be taken to EL2 at the address VBAR_EL2+offset in the EL2 address space, whereas the virtual IRQ or FIQ will be taken to EL1 at the address VBAR_EL1+offset in the EL1 address space. Even if VBAR_EL2 and VBAR_EL1 have the same values, these are in different virtual address spaces, so will be handled by different software.