Hi,
I am trying to understand if Guest OS data abort happens due to accessing some memory (e.g GIC distributor space) then is there any way I can route it to EL2 mode ?
I looked into HCR_EL2 register bits and tried setting AMO bit but it doesn't help. I see the control still reaching to EL1 Syn handler.
I would like to provide some RW memory functionality from EL2 so I want to trap it ?
Thanks.
Hi Martin,
I was trying to narrow down above problem and found one issue with Juno r0 platform.
I found that when I setup MMU at EL1 level and write MAIT_EL1 attributes to 0x000000FF440C0400 and
then write to SCTLR_EL1 to enable MMU the MAIR_EL1 properties changed to 0x000000CC440C0400 which
is causing the memory attributes at EL1 level to change. This is same happening with Linux kernel.
Only difference with bare metal and above code is that I am having my own hypervisor which is setting up vttbr
but those settings shouldn't cause above behavior ? I am not sure if it is a chip bug in Juno r0 ?
I want to confirm if there is such silicon bug exists and if there is any work around for above problem ?
When exactly do they change? If you write the register and read is back immediately, what value do you see?
I am writing MAIR_EL1 value as 0x000000FF440C0400 and I can see from DS-5 debugger this value but as soon as I enable MMU writing to SCTLR_EL1 the value in MAIR_EL1 changes to 0x000000CC440C0400 which I see in DS-5.