Is this procedure to get A53 to read/write (test) the L1D cache feasible.

I have an Xilinx Ultrascale+ device and wish to test whether the L1 Data cache has bit errors. 

Would the following ideas be feasible? 

// Idea 1: L1D data read and write.
// 0) In a baremetal helloworld app, Disable/enable/flush Dcache
// 1) Write DDR Range 1 with known data (maybe increment from 0 upwards).
// 2) Read Range 1 addresses, force caching and fill the entire L1D.
// 2.1) Compare with expected value for errors.
// 2.2) HW m/AXI may pass 64b data to register without going thru L1D?
// 3) Invert all the data and write back to those addresses.
// 3.1) Data in L1D is updated (A53 seems to use writeback policy).
// 4) Read another chunk of DDR, force L1D to evict and write back.
// 5) Read back DDR Range 1 via jtag, compare with expected data.

// Idea 2: Use CPUMERRSR.RAM_address[11:0].
// 0) In a baremetal helloworld app, Disable/enable/flush Dcache
// 1) Do some ld/st in 1 address of the L1D.
// 2) Check CPUMERRSR for error and whether the RAM_address is updated.
// 3) Iterate through 1/2 until all L1D is tested.
// 3.1) Can only locate CPUID/Way, not exact bit.

If the objective is to test the ECC of the L1D, besides register "CPUMERRSR_EL1", which is a summary of all bits. 

Is it possible to test how many bits which may contribute to 

I am aware of A53RTM: 6.7 Direct access to internal memory, but I am not sure whether it's implemented in the device itself. 

Thank you.