The ARM 64 Instruction set document lists a field "VR" under bit 26 of the LDR (literal) instruction (prior to imm 19) I am trying to find out what this field is - any pointers would be extremely helpful.
Hello,
I moved your query to the Architecture and Processors forum.
I believe this is what you are referring to:
https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LDR--immediate--SIMD-FP---Load-SIMD-FP-Register--immediate-offset--
I cannot find an explicit definition of VR, but I would assume it means Vector-Register or similar, as all these instructions apply to the SIMD registers.
Looking in the Arm Architecture reference manual:
https://developer.arm.com/documentation/ddi0487
Comparing the LDR instructions (sections C6.2.185 and C7.2.193), bit 26 is clear in the standard register version, set in the SIMD version.
Thanks Ronan, that would make sense as I am using standard registers, and the bit is cleared.