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Hi,
I have R5F core with ARMv7 architecture. I want the memory to be shared across the multiple R5F CPUs in AM2732 TI device.
I am confused what happens if -
How does the CPU distinguishes between the same ?
Best Regards,Aakash
PS. I suppose #2 should be sharable across CPUs and #4 should be done via software coherency. But what about the others really ?
Hi Martin Weidmann,
So it is okay to say that if user sets the Cacheable = 1 and Shareable = 1, then Shareable will take precedence and the processor will be provided a coherent view and the location will not be allowed to be cached.