Cacheable=0 vs Shareable=1


I have R5F core with ARMv7 architecture. I want the memory to be shared across the multiple R5F CPUs in AM2732 TI device.

I am confused what happens if -

  1. Cacheable = 1 and Shareable = 1
  2. Cacheable = 0 and Shareable = 1
  3. Cacheable = 0 and Shareable = 0
  4. Cacheable = 1 and Shareable = 0

How does the CPU distinguishes between the same ?

Best Regards,

PS. I suppose #2 should be sharable across CPUs and #4 should be done via software coherency. But what about the others really ?

  • First lets take a step back:

    The Shareable attribute is how software tells the processor who accesses this location.  Setting a location as non-shared means that software is saying that either no other observer (e.g. a DMA or other processor) will access this location, or it if does that software will deal with ensuring a coherent view.  Setting a location as shared means software is saying that some other observers might access the location AND that the processor needs to ensure a coherent view of that location.

    The Cacheable attribute is software telling the processor whether is it permitted to cache a location - I know, kind of stating the obvious.  But note, it's not a command that the location MUST be cached.  Rather that it is allowed to be cached.

    Now lets apply that to the Cortex-R5F:

    • Cacheable = 0 and Shareable = x
      • From the description above, hopefully it makes sense why Shareability doesn't really matter if the location is not cacheable.  Shareability matters in working out who is responsible for maintaining a coherent view of memory.  If the location isn't cached, that's not a problem
    • Cacheable = 1 and Shareable = 0
      • This means that location can be cached and that SW is saying no other agents/observers will access that location (or if they d, it's SW's problem).  So that's easy, the processor can cache the location and not worry about maintaining coherency.
    • Cacheable = 1 and Shareable = 1
      • This time we're saying that the location is permitted to be cached - but that other observers might access the location and we want the HW to ensure a coherent view.  Ok... so what does that mean in practice?
      • For a processor such as the Cortex-A9, that means the cache coherency logic will kick in to do the necessary steps.
      • For the Cortex-R5 - it doesn't have cache coherency logic.  So we've said that the location is permitted to be cached and we want a coherent view.  The only way the R5 can then achieve a coherent view is to not cache the location.
  • Hi ,

    So it is okay to say that if user sets the Cacheable = 1 and Shareable = 1, then Shareable will take precedence and the processor will be provided a coherent view and the location will not be allowed to be cached.

    Best Regards,