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Hello
I know there is slicon vendors implementation dependencies for the R52+ interrupt latencies, but I would like to know
a general figure for approximate and realistic minimal and maximal number of cycles for interrupt latencies in the case of the R52+ ?
I do not find any datasheet on this subject
Best Regards
Frederic
Hello, please find the Cortex-R52+ Software Consolidation white paper from the below article, which discusses this in detail for a real application.
https://newsroom.arm.com/blog/cortex-r-automotive