GIC Interrupt handling

Yes! :-)

You need to program the interrupt semantics (edge vs level) in the appropriate GICx_ICFRG<n>{E} register.  On the assumption you're interrupt source is an SPI, the register will either be GICD_ICFGR<n>:

https://developer.arm.com/documentation/ddi0601/2023-12/External-Registers/GICD-ICFGR-n---Interrupt-Configuration-Registers

Or, GICD_ICFGR<n>E:

https://developer.arm.com/documentation/ddi0601/2023-12/External-Registers/GICD-ICFGR-n-E--Interrupt-Configuration-Registers--Extended-SPI-Range- 

Note, if this is an MSI signalled via an ITS then in GIC terms it will be an LPI and LPIs are always edge.

More background info in the Learn the Architecture guide: Learn the architecture - Arm Generic Interrupt Controller v3 and v4

Yes! :-)

You need to program the interrupt semantics (edge vs level) in the appropriate GICx_ICFRG<n>{E} register.  On the assumption you're interrupt source is an SPI, the register will either be GICD_ICFGR<n>:

https://developer.arm.com/documentation/ddi0601/2023-12/External-Registers/GICD-ICFGR-n---Interrupt-Configuration-Registers

Or, GICD_ICFGR<n>E:

https://developer.arm.com/documentation/ddi0601/2023-12/External-Registers/GICD-ICFGR-n-E--Interrupt-Configuration-Registers--Extended-SPI-Range- 

Note, if this is an MSI signalled via an ITS then in GIC terms it will be an LPI and LPIs are always edge.

More background info in the Learn the Architecture guide: Learn the architecture - Arm Generic Interrupt Controller v3 and v4

uditknit said:

But this can not convert the type of interrupt , correct ? 

Correct. You need to configure the GIC to match how the device is driving the interrupt signal.

uditknit said:

1) If IP generates level trigger interrupt then GIC can be used as level or edge both 

No - that would likely cause you problems.

Let's take the Generic Timer as an example.  The timer's interrupt uses level semantics and the interrupt is driven when:

Timer Condition Met: Comparator <= System Count

The timer interrupt is cleared by either disabling the timer or updating the comparator value to a bigger number.

Now imagine the timer goes off at time X:

• X-1: Software configures interrupt as edge-triggered
  • Initial state is Inactive, Enabled, Grp1, some useful priority
• X: Timer condition met
  • Timer interrupt signal asserted to GIC
  • INTID goes from Inactive to Pending
  • INTID becomes Highest Priority Pending Interrupt and forwarded to PE
• X+1: IRQ signalled to PE
• X+2: IRQ exception taken on PE
• X+3: Software acknowledges interrupt by reading ICC_IAR1
  • INTID goes from Pending to Active
• X+4: Interrupt handling software writes new value to comparator 

Now this is the potentially problematic part - you'd assume that the new comparator value was enough into the future that the timer's interrupt condition was not met.  But that's not guaranteed and there are reasons why it might not be true.

So let's assume that in this case the new comparator value means the timer IS STILL met and therefore the interrupt signal IS STILL asserted

• X+4 cont:
  • No change to interrupt signal from timer (still asserted)
  • No change to INTID state in GIC (still Active)
• X+5: Software deactivates timer interrupt (write to ICC_DIR or ICC_EOIR1)
  
  • INTID goes from Active to Inactive.

And now we have a problem.  The timer "thinks" it is sending an interrupt to the GIC, as it's asserting a level-sensitive signal.  The GIC "thinks" there is no pending interrupt, as it "thinks" the signal is edge-triggered and it's only seen one edge.

Really the message is - software needs to program the GIC to match the sending devices.  Having a miss-match will likely cause you interesting problems to debug