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Cache maintanance operation to PoC

Luke

Hi experts,

I'm quite confused about cache maintanance operation to PoC on Cortex-A9 (with PL310 L2 cache controller).

I'm refererring to the following operations:

- DCIMVAC, invalidate data cache by MVA to POC      (mcr  p15, 0, r0, c7, c6, 1)

- DCCMVAC, clean data cache by MVA to POC           (mcr  p15, 0, r0, c7, c10, 1)

- DCCIMVAC, clean and inv data cache by MVA to POC  (mcr  p15, 0, r0, c7, c14, 1)

As far as I know, on Cortex-A9, PoC is main external system memory (RAM) and PoU is L2 cache.

So my questions/doubts are:

1) Do these operations really clean/invalidate also L2? I'm pretty sure that PL310 needs to be cleaned/invalidate by separete instrunctions. So I think that the definition "to PoC" is quite misleading.

2) What happens if L2 (PL310) is disabled?

3) On other processors where L2 cache is "on-core" (for example Cortex-A8 and Cortex-A9) do these operations have different behavior?

Could anyone please shed some light

Thanks in advance

Regards

Luke

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  • 0 Arm Employee Badge in reply to Luke

    Just for an extra bit of clarification, we had a little discussion here in the office about the meaning of this paragraph in the ARMv7-A ARM:

    • For MVA operations, two conceptual points are defined:
      • Point of coherency (PoC)
        • For a particular MVA, the PoC is the point at which all agents that can access memory are guaranteed to see the same copy of a memory location. In many cases, this is effectively the main system memory, although the architecture does not prohibit the implementation of caches beyond the PoC that have no effect on the coherence between memory system agents.

    (Our emphasis added)

    This might be considered a little unclear - it could either mean that:

    • Those caches have no 'effect' on the coherency of the system (i.e. it is maintained) in that they are handled by a combination of extra coherency logic and system barriers which will handle whether it goes to main memory (Cortex-A15 with a CCN-504 for example)
    • It can be cached in lieu of main memory with no ill effects such as an "L4" cache built in to a memory controller, such that all accesses to main memory will be filled by the cache with no ill effects (transparent caches past any coherency-maintaining logic are implicitly coherent)
    • They have no effect on the coherency of the system in that they will interfere with coherency with respect to other implementations (this is essentially anything with an L2C-310).

    We've decided that it technically means all of the above, but it is most likely intended to cover the final L2C-310-style case, where an external cache may need extra work to maintain.

    Thanks,

    Matt

Reply
  • 0 Arm Employee Badge in reply to Luke

    Just for an extra bit of clarification, we had a little discussion here in the office about the meaning of this paragraph in the ARMv7-A ARM:

    • For MVA operations, two conceptual points are defined:
      • Point of coherency (PoC)
        • For a particular MVA, the PoC is the point at which all agents that can access memory are guaranteed to see the same copy of a memory location. In many cases, this is effectively the main system memory, although the architecture does not prohibit the implementation of caches beyond the PoC that have no effect on the coherence between memory system agents.

    (Our emphasis added)

    This might be considered a little unclear - it could either mean that:

    • Those caches have no 'effect' on the coherency of the system (i.e. it is maintained) in that they are handled by a combination of extra coherency logic and system barriers which will handle whether it goes to main memory (Cortex-A15 with a CCN-504 for example)
    • It can be cached in lieu of main memory with no ill effects such as an "L4" cache built in to a memory controller, such that all accesses to main memory will be filled by the cache with no ill effects (transparent caches past any coherency-maintaining logic are implicitly coherent)
    • They have no effect on the coherency of the system in that they will interfere with coherency with respect to other implementations (this is essentially anything with an L2C-310).

    We've decided that it technically means all of the above, but it is most likely intended to cover the final L2C-310-style case, where an external cache may need extra work to maintain.

    Thanks,

    Matt

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