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I would appreciate assistance on the following:
Suppose a bus master with 128bit data width.
This master access a 64bit slave via AXI matrix as follows:
awaddr = 0x4000_909F
awsize = 0x0 (8bit write)
awlen = 0x0 (single trans)
wstrb = 0x0080;
wdata = 0xABCDEF01_10FEDCBA_12345678_87654321 (I've marked in red the relevant byte according to wstrb value)
1. Is this a valid transaction from a 128bit master to a 64bit slave?
(note that addr 0x4000_909F aims at the byte MSB of the data ; 0xAB in my example)
2. What would you expect the wstrb value on the 64bit slave.
I get wstrb = 0x00
Thank you in advanced.
You should have two write strobe values at the slave because it takes two 64-bit data beats to write a 128-bit value, so I would expect strobe 0x00 for the first beat and 0x80 for the second.
*EDIT* Sorry - ignore, I missed your write was smaller than bus width ...
HTH, Pete
Hello,
why does your AXI master have only 16 bit for wstrb?
If the data bus width is 128 bit, 32 bit is needed for wstrb.
Best regards,
Yasuhiko Koumoto.
I am sorry, I have been misunderstood.
Wstrb is 16 bit for 128 bit data bus width.
If 0xAB would be written, the wstrb of 0x0080 was incorrect.
If the wstrb is 0x0080, the address should be 0x4000_9097.
A simple AXI128-AXI64 bridge will generate 0x00 and 0x80 for the wstrb according to the data of 0x12345678_87654321 and 0xABCDEF01_10FEDCBA.