Hello everyone,
I am trying to count bus accesses from all 4 cores simultaneously. Since the BUS_ACCESS (0x19) event is not counted properly, I tried to approximate the count by adding other events.
Adding non-cacheable external memory accesses (0xC1), L2-cache refills (0x17) and L2-cache write-backs (0x18) nearly got me there, but in my 1-core test setup, this sum was still approx. 8% *lower* than the bus access count, so I was still missing something.
Here, in an official ARM documentation article, it is stated for the A53 that "BUS_ACCESS = Cacheable Traffic + Non-cacheable Traffic + Write streaming". The count I am missing should be the last summand, since those writes in read allocate mode are neither non-cacheable nor write-backs.
In the same article, the counter 0xC5 is referenced in relation to the Write streaming. The only information I could find on this event is the event name "Read allocate mode" in DDI0500J. However, the graph for this event looks really weird and does not seem to be what I need at all.
Is there any way to find more detailed information on this and other "implementation-defined" events for the A53? The name by itself is only moderatly helpful.
Thanks in advance