Hello experts,I feel I am an amateur.I tried to work the performance monitor of Cortex-A9 but it did not work.The followings are my codes.Please tell me what was wrong.
mov r3, #0 mcr 15, 0, r3, cr9, cr12, {0} // PMCR PMU disable mov r0, #0x11 // Cycle Count mov r3, #0 mov r2, #0 mov r0, #17 mcr 15, 0, r2, cr9, cr12, {5} // PMSELR PMC0 mcr 15, 0, r3, cr9, cr13, {2} // PMXEVCNTR0 zero clear mcr 15, 0, r0, cr9, cr13, {1} // PMXEVTYPER0 event set mov r0, #3 // DCache Miss mov r3, #1 mcr 15, 0, r3, cr9, cr12, {5} // PMSELR PMC1 mov r3, #0 mcr 15, 0, r3, cr9, cr13, {2} // PMXEVCNTR1 zero clear mcr 15, 0, r0, cr9, cr13, {1} // PMXEVTYPER1 event set mov r3, #0x8000003f mcr 15, 0, r3, cr9, cr12, {1} // PMCNTENSET all counters enable mcr 15, 0, r3, cr9, cr12, {3} // PMOVSR overflow flags clear mov r3, #1 mcr 15, 0, r3, cr9, cr14, {0} // PMUSERENR User mode enable mov r3, #7 mcr 15, 0, r3, cr9, cr12, {0} // PMCR PMU enable <<Target Program to be measured the performance >> mov r3, #0 mcr 15, 0, r3, cr9, cr12, {0} // PMCR PMU disable mov r0, #0 mcr 15, 0, r0, cr9, cr12, {5} // PMSELR PMC0 mrc 15, 0, r0, cr9, cr13, {2} // PMXEVCNTR0 read << the r0 value is 0!!>> mov r0, #1 mcr 15, 0, r0, cr9, cr12, {5} // PMSELR PMC1 mrc 15, 0, r0, cr9, cr13, {2} // PMXEVCNTR1 read << the r0 value is 0!!>>
Thank you and best regards,Yasuhiko Koumoto.
Hello all,
after some experiments, I found PMCCNTR worked but the other event counters did not work.
According to Cortex-R5F TRM section 6.2, the following descriptions exist.
The PMU only counts events when non-invasive debug is enabled, that is, when either
DBGENm or NIDENm inputs are asserted. The Cycle Count (PMCCNTR) Register is always
enabled regardless of whether non-invasive debug is enabled, unless the DP bit of the PMCR
register is set.
If it is true, cannot I use the performance event counters unless a debugger was connected.
Best regards,
Yasuhiko Koumoto.
Hello,
my colleague of a certain ICE maker investigated the problem.
As the results, my board COMPUTEX CEV-RZ/A1L does not support the performance monitoring if not connected to a JTAG debugger, although almost all Cortex-A9 SBC will work the performance monitor without a debugger.
This will be consistent with my previous post.
The JTAG related pins would be specially treated on my board.
Can anyone explain by what reason why PMU will be disabled?
I would like to know the solution to enable PMU without any debuggers.
Thank you and best regards,
I will close this issue as there are no responses.
As for now, I can use the performance monitor with the debugger.
Although I have no clear reason, I would compromise with it.