Hi,
As per the title says, I'm getting an unaligned memory access fault with an STRH instruction. I know the memory referenced in the instruction is unaligned, but I only expected a performance penalty, not a hard fault. Instruction that causes the error:
strh r7, [r0, #4]
Register values:
Have added before/after register values for SCB.
What have you got in CCR? It's got a config bit:
UNALIGN_TRP, bit[3]
Controls the trapping of unaligned word or halfword accesses:
0 Trapping disabled.
1 Trapping enabled.
Unaligned load-store multiples and word or halfword exclusive accesses always fault.
Thanks for the suggestion. That bit is already set to 0, was one of the first things I checked.