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ARM Cortex-R7 :: MPU Region Access Control Register (DRACR) Documentation

andreasn

Hi all,

there is a remarkable difference in the encoding of the MPU Region Access Control Register setting (DRACR) documentation in :

- the (actual) TRM : DDI0458D_cortex_r7_trm.pdf (TRM Rev D. Dec 2016)
compared with the (actual) architecture refernce manual : DDI0406C_d_armv7ar_arm.pdf (29 March 2018 )


Table 8-2 TEX[2:0], C, and B encodings (page 152 DDI0458D_cortex_r7_trm.pdf)

TEX[2:0] C B Description Memory type Shareable?
--------------------------------------------------------------------
000 0 0 Strongly Ordered. Strongly Ordered Shareable
000 0 1 Shareable Device. Device Shareable
000 1 0 Reserved. - -                                                                << "Reserved" for TEX = 000, C = 1, B = 0
                                                                                                  << encoding for "000 11" missing
001 0 0 Outer and Inner Non-cacheable. Normal S bit
..


Table B5-4 C, B and TEX[2:0] encodings (page 1754 in DDI0406C_d_armv7ar_arm.pdf)

TEX[2:0] C B Description Memory type Shareable?
--------------------------------------------------------------------
000 0 0 Strongly-ordered Strongly-ordered Shareable
000 0 1 Shareable Device Device Shareable


000 1 0 Outer and Inner Write-Through, no Write-Allocate Normal S bita                            << "normal" write through for TEX = 000, C = 1, B = 0
000 1 1 Outer and Inner Write-Back, no Write-Allocate Normal S bita                                  << "normal" write back for TEX = 000, C = 1,  B = 1

001 0 0 Outer and Inner Non-cacheable Normal S bita
..

Which documentation is correct for the CortexR7 ?

Parents
  • 0

    In CR7 TRM, it is mentioned that the Write-Through cache policy is not supported.
    CR7 does not support Write Back no Write-Allocate.  All Inner Write-Back memory is treated as Write-Back Write-Allocate ignoring any cache allocate hint, though this can dynamically switch to no Write-Allocate, if more than three full cache lines are written in succession.

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  • 0

    In CR7 TRM, it is mentioned that the Write-Through cache policy is not supported.
    CR7 does not support Write Back no Write-Allocate.  All Inner Write-Back memory is treated as Write-Back Write-Allocate ignoring any cache allocate hint, though this can dynamically switch to no Write-Allocate, if more than three full cache lines are written in succession.

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