Hello,
I have a question if following sequence of instructions involving post-indexed LDRs could be re-ordered on say Cortex A8:
To simplify, lets consider, r0 = 0xC, Cache line size 16 Bytes
ldr r1, [r0], #4 /* 1 */
ldr r2, [r0], #4 /* 2 */
ldr r3, [r0], #4 /* 3 */
ldr r4, [r0], #4 /* 4 */
/* At this point, r0 = 0x1C */
Now, will the above instructions always be executed in order 1-2-3-4 (because r0 is getting updated across) or there are chances that it could execute as 2-3-4-1 etc?
Thanks.
It would depend on what kind of an abort it was.
For MMU based faults (translation fault, permission faults, access flag faults...) these are synchronous with the instruction that caused them. And as mentioned, instructions must appear to be executed in order.
For the instruction sequence you gave, imagine that the starting value of r0 was 0x3FFF,FFF8. That is, the first to instructions access one page (page A) and the next two access the following page (page B).
Let's say page A is marked as Fault and page B as Normal. The first LDR will trigger a synchronous fault. The processor _might_ have speculatively already performed the two loads from page B, but when we take the exception the state will be consistent with none of the later instructions having executed.
Thanks a lot, that clarifies!