Hello,
I have a question if following sequence of instructions involving post-indexed LDRs could be re-ordered on say Cortex A8:
To simplify, lets consider, r0 = 0xC, Cache line size 16 Bytes
ldr r1, [r0], #4 /* 1 */
ldr r2, [r0], #4 /* 2 */
ldr r3, [r0], #4 /* 3 */
ldr r4, [r0], #4 /* 4 */
/* At this point, r0 = 0x1C */
Now, will the above instructions always be executed in order 1-2-3-4 (because r0 is getting updated across) or there are chances that it could execute as 2-3-4-1 etc?
Thanks.