ARM Context ID Register & Process Context Switch

Yes, it is the OS which is responsible for assigning ASIDs to processes.

It depends on what you mean by essential.  ASIDs allow TLB entries to be tagged as belonging to a specific process.  This means you don't need to invalidate the TLBs when context switching between different processes (as each has it's own ASID, and thus their TLB entries can be told apart).  This not only saves you from an unnecessary invalidate, but means that you can potentially pick up the TLB entries when next the process is context switched back in.

It's not strictly essential that you use ASIDs.  You could just invalidate the TLB on each context switch instead.  However, this would be less efficient.

The Context ID register is present on all ARMv7-A processors, including the Cortex-A8.  It works in the same way on the Cortex-A8 and Cortex-A9.

LPAE (implement on Cortex-A7, Cortex-A15 and Cortex-A17 + all ARMv8-A processors) changes where the ASID is stored.  But the basic mechanism stays the same.

Yes, it is the OS which is responsible for assigning ASIDs to processes.

It depends on what you mean by essential.  ASIDs allow TLB entries to be tagged as belonging to a specific process.  This means you don't need to invalidate the TLBs when context switching between different processes (as each has it's own ASID, and thus their TLB entries can be told apart).  This not only saves you from an unnecessary invalidate, but means that you can potentially pick up the TLB entries when next the process is context switched back in.

It's not strictly essential that you use ASIDs.  You could just invalidate the TLB on each context switch instead.  However, this would be less efficient.

The Context ID register is present on all ARMv7-A processors, including the Cortex-A8.  It works in the same way on the Cortex-A8 and Cortex-A9.

LPAE (implement on Cortex-A7, Cortex-A15 and Cortex-A17 + all ARMv8-A processors) changes where the ASID is stored.  But the basic mechanism stays the same.

Just to expand on Martin's post:

• For pre-LPAE processors and later processors using "Short-descriptors", the ASID is stored in the least-significant byte of the CONTEXTIDR register. The rest of the register is not used by the MMU.
• For processors using LPAE's "Long-descriptors", the ASID is stored elsewhere, and the CONTEXTIDR is not used by the MMU.

ASIDs allow virtual addresses to be tagged to a process, as Martin describes.

The (portion of the) CONTEXTIDR not used by the MMU is used for debug. E.g. you can tag hardware breakpoints/watchpoints to match on CONTEXTIDR, and ETM trace outputs CONTEXTIDR. The value in the register has no other meaning to the hardware. It is up to the OS to assign a useful value to this for debugging.

The ASID on the ARM is by my opinion badly designed. It should be possible to store it also in the page-table. On PowerPC E200 cores, one can directly write the TLB and set the ASID. Why ARM did not extend the page-table entries to hold also an ASID is still a big mystery to me.

I wonder, is there really no way (hidden bit) to disable hardware table walk and write TLB entries directly?

It would be good if you gave reasons for what you say and for what you want to do. It would probably be better to start up a a separate discussion as it seems to not be closely related to this one.