Hi, I'm reading SCTLR bit fields and have 3 questions.
1. In these bit fields (AFE, TRE, UWXN, WXN), there are comments like 'The AFE bit is permitted to be cached in a TLB.'
I can't figure out what the meaning of 'permitted to be cached in a TLB' comment.
I guess this comment means TLB implementor can decide whether TLB has these additional bits for speed up or not.
2. And want to know the difference between UWXN and WXN, I'm very confusing about these two.
3. In the manual, there is some restriction for a stage 1 translation table walk like as below.
If the value of SCTLR.M is 0, instruction accesses from stage 1 of the PL1&0
translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer
Write-Through memory.
I think stage 1 is, for a section, calculation of address from VA to PA.
For a small page, stage 1 is from VA to page table entry and stage 2 is from it to PA.
Why is the restriction for just stage 1? I believe second level page table also must be a Normal type, not a Device type.
What's the difference between stage 1 and stage 2 translation table walk?
Umm number 3 means that what is the meanning of stage 1 translation table walk in armv8 specification.
Ahh, I think I understand now.
You're correct that stage 1 means VA to IPA*, and stage 2 means IPA to PA.
When the stage 1 MMU is disabled, the processor has to treat memory accesses as something. The architecture says that instruction fetches are treated as Normal and data accesses as Device. This isn't really a restriction, more of a default until you get the MMU enabled.
There isn't really an equivalent for set of defaults for stage 2, so by that time you've already gone through stage 1. And will have the attributes from the stage 1 translation (either from coming from the tables, or the defaults).
(If there is no 2nd stage, IPA==PA)