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Hi, I'm reading SCTLR bit fields and have 3 questions.
1. In these bit fields (AFE, TRE, UWXN, WXN), there are comments like 'The AFE bit is permitted to be cached in a TLB.'
I can't figure out what the meaning of 'permitted to be cached in a TLB' comment.
I guess this comment means TLB implementor can decide whether TLB has these additional bits for speed up or not.
2. And want to know the difference between UWXN and WXN, I'm very confusing about these two.
3. In the manual, there is some restriction for a stage 1 translation table walk like as below.
If the value of SCTLR.M is 0, instruction accesses from stage 1 of the PL1&0
translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer
Write-Through memory.
I think stage 1 is, for a section, calculation of address from VA to PA.
For a small page, stage 1 is from VA to page table entry and stage 2 is from it to PA.
Why is the restriction for just stage 1? I believe second level page table also must be a Normal type, not a Device type.
What's the difference between stage 1 and stage 2 translation table walk?
Number 3 question.
I guess page 3522 (Mixed-endian support) explain some register like CPSR, SCTLR, HSCTLR.
CPSR (Explicit data accesses), SCTLR (Stage 1 Translation table walks), HSCTLR (Stage 2 Translation table walks)
So I guess Stage means like EL? or PL? Actually operating system stage 1 translation, hiper-visor also use mmu this translation walks describe stage 2 hehe.
sorry this comment only my guess..!!
1. In these bit fields (AFE, TRE, UWXN, WXN), there are comments like 'The AFE bit is permitted to be cached in a TLB.' I can't figure out what the meaning of 'permitted to be cached in a TLB' comment. I guess this comment means TLB implementor can decide whether TLB has these additional bits for speed up or not.
These bits affect how the contents of the translation tables are interpreted. For example, when UWXN/WXN==1 address with write permission are treated as XN (eXecute-Never), regardless of the value of the PXN/UXN bits in the translation table entry.
The TLBs store the resulting translation. They would be permitted to store that the address was XN - but not required to store why it was XN (i.e. XN due UWXN/WXN). Therefore if you changed the setting of UWXN/WXN you would also need to invalidate the TLBs.
UWXN means for Unprivileged Write permission implies eXecute Never. When UWXN=1, if the address is writeable in User mode (EL0), then the address is XN in EL1 modes (e.g. SVC mode). It can be used to prevent a kernel from executing from User space write-able memory.
WXN stands for Write permission implies eXecute Never. When WXN=1, if the address is writeable it is not executable (at either EL0 or EL1).
NOTE: if EL1 uses AArch64, when the stage 1 MMU is enabled, any address writeable at EL0 is always treated as XN for EL1.
3. In the manual, there is some restriction for a stage 1 translation table walk like as below. If the value of SCTLR.M is 0, instruction accesses from stage 1 of the PL1&0 translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer Write-Through memory.
Not sure what your question is. The text you quoted is about the behavior when the the MMU is disabled. Which is that instruction fetches are treated as "Normal" type.
Umm number 3 means that what is the meanning of stage 1 translation table walk in armv8 specification.
Ahh, I think I understand now.
You're correct that stage 1 means VA to IPA*, and stage 2 means IPA to PA.
When the stage 1 MMU is disabled, the processor has to treat memory accesses as something. The architecture says that instruction fetches are treated as Normal and data accesses as Device. This isn't really a restriction, more of a default until you get the MMU enabled.
There isn't really an equivalent for set of defaults for stage 2, so by that time you've already gone through stage 1. And will have the attributes from the stage 1 translation (either from coming from the tables, or the defaults).
(If there is no 2nd stage, IPA==PA)