The madman strikes again - ADD/SUB SP

Is there something special in the instructions ADD (SP plus register, ARM) and SUB (SP minus register)?

I didn't find anything different from the basic ADD  (register) and SUB (register) except the documentation:

<Rd> The destination register. If S is specified and <Rd> is the PC, see SUBS PC, LR and related

instructions (ARM) on page B9-2012. This register can be SP. If omitted, <Rd> is SP. This register

can be the PC, but ARM deprecates using the PC.

If S is not specified and <Rd> is the PC, the instruction is a branch to the address calculated by the

operation. This is an interworking branch, see Pseudocode details of operations on ARM core

registers on page A2-47. ARM deprecates this use of the PC.

Yet in the pseudocode:

(result, carry, overflow) = AddWithCarry(SP, shifted, ‘0’);

if d == 15 then

ALUWritePC(result); // setflags is always FALSE here

And nothing in the errata.

If Rd is PC, then the result is written into SP, and the program jumps to the address?

With any other register (than PC) as Rd, the Rd is ignored and the result is written into SP?