Is there something special in the instructions ADD (SP plus register, ARM) and SUB (SP minus register)?
I didn't find anything different from the basic ADD (register) and SUB (register) except the documentation:
<Rd> The destination register. If S is specified and <Rd> is the PC, see SUBS PC, LR and related instructions (ARM) on page B9-2012. This register can be SP. If omitted, <Rd> is SP. This register can be the PC, but ARM deprecates using the PC. If S is not specified and <Rd> is the PC, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode details of operations on ARM core registers on page A2-47. ARM deprecates this use of the PC.
<Rd> The destination register. If S is specified and <Rd> is the PC, see SUBS PC, LR and related
instructions (ARM) on page B9-2012. This register can be SP. If omitted, <Rd> is SP. This register
can be the PC, but ARM deprecates using the PC.
If S is not specified and <Rd> is the PC, the instruction is a branch to the address calculated by the
operation. This is an interworking branch, see Pseudocode details of operations on ARM core
registers on page A2-47. ARM deprecates this use of the PC.
Yet in the pseudocode:
(result, carry, overflow) = AddWithCarry(SP, shifted, ‘0’); if d == 15 then ALUWritePC(result); // setflags is always FALSE here
(result, carry, overflow) = AddWithCarry(SP, shifted, ‘0’);
if d == 15 then
ALUWritePC(result); // setflags is always FALSE here
And nothing in the errata.
If Rd is PC, then the result is written into SP, and the program jumps to the address?
With any other register (than PC) as Rd, the Rd is ignored and the result is written into SP?
Hi turboscrew,
Symmetry of documentation is probably the reason - documenting the strange Thumb encoding and not specifying an ARM encoding for the exact same operation (even if ADD{S} covers it with r13 as Rn) means it isn't 100% obvious as to why that extra Thumb instruction exists. It also has some very, very specific behaviour when PC is Rd which bears documenting - even though it's deprecated to use that behaviour. Most of the uses regarding the PC are all to do with using the stack as a dynamic veneer/trampoline. ADDS PC, SP, RX makes very little sense, but there are some very interesting exception return possibilities from System mode possible, for example (an OS causing the next BX LR to execute code from the stack..). Using the SP like this got almost blanket deprecated in later versions of the Architecture (see the end of the ARM ARM, section D9.3) because there are better ways to do it, or no way of encoding them as a Thumb instruction - they're essentially concessions to UAL with extra cleaning power for the instruction set definition
Ta,
Matt
Yes, I have noticed the abundance (an understatement) of ways of returning from an exception.