In the SSAT instruction description it says:
ASR #32 Arithmetic right shift by 32 bits, permitted only for encoding A1. Encoded as sh = 1, immsh = 0b00000.
ASR #32 Arithmetic right shift by 32 bits, permitted only for encoding A1.
Encoded as sh = 1, immsh = 0b00000.
What does that mean?
Isn't ASR #32 the same as ASR #31?
I understand that it shifts (with "sign extension") the whole 32-bit value out and leaves only the sign extension bits
that are "copies" of the highest bit of the original value.
What am I missing here?
Starting from the msb end, it goes something like ... [A/L]SRS : RRX : RRX : RRX : RRX : ... : RRX
That's what I thought - longer shifts won't work.
BTW, nice post (the Cortex-M0 tricks).
I was rather thinking about uqadd16, uxtab, qdadd, and the like.
Not used in every program.
Well I was thinking of something simple like testing the top two bits of a register. (I haven't tested this)
MOVS r0, r1, ASR #31
BHI starts_11 ; Z clear C set
BMI starts_10
BCS starts_01
... starts_00
using MVNS you can test for 01 first.
p.s. I don't think this sort of thing makes for happy colleagues though it might ensure a living for years to come.
That definitely qualifies for a cool trick. If you want to avoid branching, you could combine it with the sbcs instruction like SBCS r3,r3,r3 after a BMI.
(or of course use conditional execution). Using it as a mask for a conditional AND would probably also be useful.
... MVNS r0,r1,asr#31 might also prove useful, if you need to invert the sign.