Architectures and Processors forum Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?

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Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?

Kun.Niu over 10 years ago

Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?

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daith over 10 years ago +1 verified

Yes. They start off after a reset in the same sort of state and get the same inputs, the outputs are compared and if there is a difference there is a system error and they're out of step. I think normally...