Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?

Yes. They start off after a reset in the same sort of state and get the same inputs, the outputs are compared and if there is a difference there is a system error and they're out of step. I think normally they share a single cache with ECC rather than having two caches. There's a Wikipedia article about it

Dual modular redundancy - Wikipedia, the free encyclopedia

The Space Shuttle had four computers doing this and  a fifth backup one. It worked using a majority vote if one failed. And it had to abort the first launch because of a problem in synchronizing the computers - what happens in the 'reset' bit I mentioned above. There was a course on reliability at the time, they studied the Shuttle computer system as part of that and took time off to watch the launch. "That's the bit we were just saying could be a problem" they said as they heard the background talk during the launch - and then came the news it was aborted.

Yes and No. Mostly the second core is delayed a bit (IIRC, for TI's TMS570/RM4 it is half a clock cycle).

The reason is, that external effects (e.g. radiation) does not disturb both cores in the same state.