In AXI5 Atomic Transaction is there a facility that we can send address or data first?
Hey ash11
The Community help forum is for questions on how to use the community. Please take a look at https://community.arm.com/support-forums/ and let me know which support forum I can move this question to.
Many thanks
Oli
Arm Community team
Hi Oliver, Can you please this question to AXI ?
We don't have a specific AXI forum, unless you mean something else?
Architectures and Processors.
I suppose an exclusive access monitor doesn't really care when the write data is seen as all it cares about is comparing the write address against a stored read address, so if the write data came before the write address, this doesn't affect the exclusive access monitor operation.
It would though be an issue for the target device to resolve, not knowing what to do with the write data until it sees an address, so the target might hold WREADY low until it has received the address, or it might be able to buffer up the write data until it knows what to do with it.
The AXI protocol allows write data before write address, so I can't see how this would be an issue for the exclusive monitor logic.
Not quite sure what you mean by "is there a facility".
So you mean we can't send data first in case of atomic transaction. As we can send as in normal writen transaction?
I'd say the opposite, that you could send write data first.
The write data transfer isn't really relevant to the successful completion of the exclusive sequence, it would be the write address that is checked against other accesses.
But where leading write data would then be an issue is at the destination, where without an address you don't know what to do with that data. So the destination device might either buffer that write data, or it might hold WREADY low to stall the write data. But neither of them are relevant to the exclusive access mechanism.
So an exclusive write is just the same as a normal write, except that it must be preceded by a matching exclusive read, and obviously that it will have monitoring logic that might change the write response returned.
But that's all theoretical. The physical implementation of an exclusive access monitor might want to delay the W channel transfer completing until it has seen and checked the AW transfer, just to make things simpler or cleaner to process.