Hello experts,
I would like to ask the reason why the exception frame forms on PSP in the Cortex-M architecture.My understanding is that MSP (Main Stack Pointer) is the interrupt stack pointer and PSP (Porcess Stack Pointer) is the normal (user) stack pointer.From my little experiences, the exception frame was formed on the interrupt stack.However, the ARM forms it on the user stack.
Best regards,Yasuhiko Kouoto.
Hello daith,
thank you for your patient explanations.
I have now almost understood what you had said.
However, I wonder one thing.
In a case of a context switch, why are the registers on the stack (e.g. MSP or PSP) referred? I think to use STM or LDM is more convenient.
How do you think?
Best regards,
Yasuhiko Koumoto.
I'm not sure I've understood you properly - sorry. Yes I very much suppose they various registers would be saved or loaded using LDM and STM instructions. It is a place where one can't get away with just C code unfortunately.
my concerning point is that I guess the context switch routine will be written by assembler.In the case, the software can directly save the current registers to the appropriate area other than LR, PC and xPSR.If this is correct, it will be convenient if those registers (i.e. LR, PC and xPSR) are on MSP rather than PSP.If they are on PSP, the software should check where they exist on MSP or PSP.Therefore, I feel it is really advantage which some contexts are saved on PSP.Although I basically understand what you say, I cannot believe it will be for the context switch that some contexts are saved on PSP.
Best regards,Yasuhiko Koumoto.