The cortex-A7's pipeline support dual-issue, so I want to ask what's the dual-issue mean?
I find some answers say that dual-issue means that the cortex-A7 can issue two instructions per clock.
But in the cortex-A7's pipeline diagraph, it has integer, multiply, floating-pointing/NEON, dual issue, load/store.
I also want to ask the dual issue there refers to what? It has what fuction or how it works?
Hello,
although the execution pipeline has 5 ports (i.e. integer, multiply, FP/NEON, dual-issue and load/store), the Cortex-A7 has the combination of two instructions which can be provided into these ports simultaneously.
Probably the "Dual Issue" pipe would be the simple integer or branch pipe and the Cortex-A7 can issue two instructions to the "Dual Issue" pipe and another pipe at the maximum at the same time when it can be possible.
For your information, the below is the Cortex-A7 pipeline slide which was shown at the "ARM Technical Symposia 2011 Japan".
The Japanese explanation indicates the "Dual Issue" means "in-order pipeline which can be issued two instructions".
Best regards,
Yasuhiko Koumoto.
Thanks very much for your answer!
The "dual issue" pipe can only deal with simple instructions such as interger or branch instructions. Is this understand right?
I don't know because it was not disclosed by ARM.
Best regards.
according to GCC source code for Cortex-A7 (gcc/cortex-a7.md at master · gcc-mirror/gcc · GitHub), the following commens exist.
However, it would not be the official information from ARM,
;; A direct branch can dual issue either as younger or older instruction, but branches cannot dual issue with branches. No latency as there is no result.;; Call cannot dual-issue as an older instruction. It can dual-issue as a younger instruction, or single-issue. Call cannot dual-issue with another branch instruction. The result is available the next cycle.;; ALU instruction with an immediate operand can dual-issue.;; ALU instruction with register operands can dual-issue with a younger immediate-based instruction.