IO coherency

Hi Surabhi,

I think this refers to the Cortex-R5 Accelerator Coherency Port (ACP).

This is an AXI port where you can connect a peripheral. The ACP port will provide coherency between the CPUs and the peripheral. In the case of the Cortex-R5, the peripheral writes will invalidate cache lines from the CPUs caches.

See the ACP chapter in the Cortex-R5 Technical Reference Manual.

Hi Surabhi,

I think this refers to the Cortex-R5 Accelerator Coherency Port (ACP).

This is an AXI port where you can connect a peripheral. The ACP port will provide coherency between the CPUs and the peripheral. In the case of the Cortex-R5, the peripheral writes will invalidate cache lines from the CPUs caches.

See the ACP chapter in the Cortex-R5 Technical Reference Manual.