We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found
an answer to in ARMv7-A/R ARM Issue C.
How is this special?
Under which sub-chapter of A4 this fits best?
How about this:
A8.8.312
About these (what's the Rt's role) I already asked in another thread.
These are the sub-chapters:
branches
Data-processing instructions
Standard data-processing instructions.
Shift instructions on page A4-167.
Multiply instructions on page A4-167.
Saturating instructions on page A4-169.
Saturating addition and subtraction instructions on page A4-169.
Packing and unpacking instructions on page A4-170.
Parallel addition and subtraction instructions on page A4-171.
Divide instructions on page A4-172.
Miscellaneous data-processing instructions on page A4-173.
Status register access instructions
Load/store instructions
Load/store multiple instructions
Miscellaneous instructions
Exception-related instructions
Coprocessor instructions
Advanced SIMD and Floating-point load/store instructions
Extension register load/store instructions
Element and structure load/store instructions
Advanced SIMD and Floating-point register transfer instructions
Advanced SIMD data-processing instructions
Advanced SIMD parallel addition and subtraction
Bitwise Advanced SIMD data-processing instructions
Advanced SIMD comparison instructions
Advanced SIMD shift instructions
Advanced SIMD multiply instructions
Miscellaneous Advanced SIMD data-processing instructions
Floating-point data-processing instructions
Hello,
How is this special? LDRD<c>_<Rt>,_<Rt2>,_<label>_LDRD<c>_<Rt>,_<Rt2>,_[PC,_#-0]_Special_case A1 A8.8.73
In ARM case,
LDRD<c> Rt, Rt2, <label>
is the same as
LDRD<c> Rt, <label>.
Rt should be the even number register. Also, Rt2 should be R(t+1).
In Thumb case,
Rt and Rt2 can be taken as arbitrary registers.
I don't know why
LDRD<c> Rt. Rt2, [PC,#-0]
is mentioned.
Its function is the smae as
LDRD<c> Rt, Rt2, [PC, #0]
but the encoding is different because 'U' bit differs.
I don't know why the imm=0 case is specially mentioned, either.
Under which sub-chapter of A4 this fits best? MOVW<c>_<Rd>,_#<imm12> A2 A8.8.102
This is the instruction to put #imm16 into Rd[15:0].
This is used by combining with MOVT to put 32 bit immediate into the register.
I am sorry but I cannot understand what you want to ask.
How about this: VDIV<c>.F64_<Dd>,_<Dn>,_<Dm>_VDIV<c>.F32_<Sd>,_<Sn>,_<Sm> T1/A1 A8.8.312
This is the normal floating point division instruction.
In Thumb case, F64 is only support by Cortex-M7.
About these (what's the Rt's role) I already asked in another thread. PUSH<c>_<registers>,_<Rt> A2 A8.8.133 POP<c>_<registers>,_<Rt> A2 A8.8.132
These are the instructions to push or pop of only one register (i.e. Rt).
It is the same as
STR<c> Rt, [SP,#-4]!
for PUSH case.
Also it the same as
LDR<c> Rt, [SP], #4
for POP case.
I guess that these instructions are faster executed than the push or pop of several registers,
e.g. STMDB<c> SP!, {Rt} or LDMIA<c> SP!, {Rt}.
Best regards,
Yasuhiko Koumoto.
Thanks for explaining.
The reason I'm asking is that I'm trying to write a gdb stub, and finding out the next instruction for single stepping requires instruction decoding (to a point), so I want to figure out how to organize the decoding in a reasonable way.
I've already found that there are aliases in the document treated as "native" instructions and some instructions "turn" into other instructions if a register is PC or if immediate value is zero and the like.
Like shifted register MOV or RRX.
(Darn, I seem to have forgotten to mark this thread as a question.)