We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?
As usual, we talk about cache is mainly refer to the cache inside CPU, but AXI's cache or buffer is reffer to the cache inside CPU or just the cache or buffer inside
the AXI interconnect? or other place's cache or buffer?
I am looking forward for your answer, thanks very much!
Hello,
I cannot understand the purpose of your question. Do you want to know how the cacheable and bufferable attributes inherit to the system (or L2) cache?
Basically the C bit and B bit of the MMU descriptors when MMU is enabled propagate to the ARCACHE or AWCACHE signal of the system AXI bus. The encodeng is below.
Basically the bit 0 is B bit and the bit 1 is C bit ( the bit 2 indicates the read allocate and the bit 3 indicates the write allocate).
The L2 cache will act according to the ARCACHE or AWCACHE signal.
However, by my experience of ARM11 MPCore, the C bit or B bit of the MMU descriptor is not directly reflect to ARCACHE or AWCACHE signal, and some encoding was made. That is, the combination of the C bit and B bit are converted to different way.
As of now, I forgot how the encoding had been done.
I hope it will help you.
Best regards,
Yasuhiko Koumoto.
Thanks very much for your answer, its helpful to me.