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Bit 22 in some LD/ST instructions (Cortex-A7)

Juha Aaltonen

I wonder if the bit 22 has some function in instructions like LDRH, STRH, LDRSBT, LDRD, ... (bits 27, 26, 25 = 0, 0, 0)?

                           22
c c c c 0 0 0  0  U 1  1  0 n n n n t t t t x x x x 1 0 1 1 x x x x STRHT<c> <Rt>,[<Rn>],{,#+/-<imm8>}  A1  A8.8.219
c c c c 0 0 0  0  U 1  1  1 n n n n t t t t x x x x 1 0 1 1 x x x x LDRHT<c> <Rt>,[<Rn>],{,#+/-<imm8>}  A1  A8.8.83
c c c c 0 0 0  0  U 1  1  1 n n n n t t t t x x x x 1 1 0 1 x x x x LDRSBT<c> <Rt>,[<Rn>],{,#+/-<imm8>}  A1  A8.8.87
c c c c 0 0 0 (1) U 1 (0) 0 1 1 1 1 t t t t x x x x 1 1 0 1 x x x xLDRD<c> <Rt>,<Rt2>,<label> LDRD<c> <Rt>,<Rt2>,[PC,#-0]  A1  A8.8.73
c c c c 0 0 0  P  U 0  W  0 n n n n t t t t (0) (0) (0) (0) 1 1 0 1 m m m m> LDRD<c> <Rt>,<Rt2>,[<Rn>,+/-<Rm>]{!} LDRD<c> <Rt>,<Rt2>,[<Rn>],+/-<Rm>  A1  A8.8.74

In some instructions, like LDR, STR, LDRB (bits 27, 26, 25 = 0, 1, 1) , I understand, it chooses between byte and word access.

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  • 0 in reply to Yasuhiko Koumoto

    I always thought of [r1,#imm] as being indexed, just as a constant index.

    But it would be more correct to call it immediate and the base register + index register for indexed mode.

    -There are a few more modes:

    pre-increment / pre-decrement (aka pre-update):

         ldr     r0,[r1,#10]!

    post-increment / post-decrement (aka post-update):

         ldr     r0,[r1],#10

    The following two are allowed in the older ARM architectures, but unfortunately not in thumb or thumb2:

         ldr     r0,[r1,r2]!

         ldr     r0,[r1],r2!

    -The post-update would have been particularly useful for me, particularly when being able to use them with LSL, LSR and ASR#16.

    But as the Cortex is clocked higher, it will still outperform the older architectures even when adding the extra add instruction (which is "for free" on the Cortex-M7 by the way).

Reply
  • 0 in reply to Yasuhiko Koumoto

    I always thought of [r1,#imm] as being indexed, just as a constant index.

    But it would be more correct to call it immediate and the base register + index register for indexed mode.

    -There are a few more modes:

    pre-increment / pre-decrement (aka pre-update):

         ldr     r0,[r1,#10]!

    post-increment / post-decrement (aka post-update):

         ldr     r0,[r1],#10

    The following two are allowed in the older ARM architectures, but unfortunately not in thumb or thumb2:

         ldr     r0,[r1,r2]!

         ldr     r0,[r1],r2!

    -The post-update would have been particularly useful for me, particularly when being able to use them with LSL, LSR and ASR#16.

    But as the Cortex is clocked higher, it will still outperform the older architectures even when adding the extra add instruction (which is "for free" on the Cortex-M7 by the way).

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