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I wonder if the bit 22 has some function in instructions like LDRH, STRH, LDRSBT, LDRD, ... (bits 27, 26, 25 = 0, 0, 0)?
In some instructions, like LDR, STR, LDRB (bits 27, 26, 25 = 0, 1, 1) , I understand, it chooses between byte and word access.
I always thought of [r1,#imm] as being indexed, just as a constant index.
But it would be more correct to call it immediate and the base register + index register for indexed mode.
-There are a few more modes:
pre-increment / pre-decrement (aka pre-update):
ldr r0,[r1,#10]!
post-increment / post-decrement (aka post-update):
ldr r0,[r1],#10
The following two are allowed in the older ARM architectures, but unfortunately not in thumb or thumb2:
ldr r0,[r1,r2]!
ldr r0,[r1],r2!
-The post-update would have been particularly useful for me, particularly when being able to use them with LSL, LSR and ASR#16.
But as the Cortex is clocked higher, it will still outperform the older architectures even when adding the extra add instruction (which is "for free" on the Cortex-M7 by the way).
Hello jensbauer,
thank you for your comments.
If we consider about the pre-indexed or post-indexed, it would be reasonable to take the immediate for the index.
Therefore, we should call it as the immediate indexing or the register indexing, shouldn't we?
Best regards,
Yasuhiko Koumoto.
yasuhikokoumoto wrote: Therefore, we should call it as the immediate indexing or the register indexing, shouldn't we?
yasuhikokoumoto wrote:
I agree. If we do that, then there will be no doubt what we mean. I will start practicing this.